Philips Stereo System PNX2000 User Manual

PNX2000  
Audio video input processor  
Rev. 03 – 23 August 2004  
Product data  
1. General description  
The PNX2000 is a companion IC for use with the Nexperia™ 1 digital video home  
entertainment engines such as PNX8526 and PNX8550.  
The PNX2000 is always used in combination with the PNX3000.  
PNX2000 is intended for mid to high-end analog and hybrid TV sets, performing input  
decoding of single stream analog audio and single stream analog video signals. In  
addition, the PNX2000 is used for decoding and presentation of all audio output streams  
in the system. Figure 1 shows a block diagram of the device.  
2. Features  
Detection of PAL, NTSC or SECAM, and various 1fH and 2fH component video input  
sources.  
Full support for 1fH and 2fH video sources; progressive and interlaced.  
Decoding for global VBI Standards (WST, WSS, VPS, CC, VITC).  
ITU-656 output interface.  
Global multi-standard audio demodulation and decoding.  
Dolby Pro Logic II™ 2 multi-channel audio decoding and post-processing.  
Advanced fully programmable audio post-processing functions, including  
psychoacoustic spatial algorithms for optimal loudspeaker matching.  
3. Applications  
Analog TV receivers.  
Hybrid TV receivers.  
DVD recorders.  
VCRs.  
1. Nexperia is a trademark of Koninklijke Philips Electronics N.V.  
2.  
Dolby is a trademark of Dolby Laboratories  
 
     
PNX2000  
Philips Semiconductors  
Audio video input processor  
6. Pinning information  
6.1 Pinning  
1
108  
PNX2000HL  
36  
73  
001aaa287  
Fig 2. Pin configuration  
6.1.1 Pin description  
Table 2 describes acronyms used in the pin tables:  
Table 2:  
Acronym  
3V  
Acronym description  
Description  
3.3 V LVCMOS  
5 V tolerant inputs  
3-state  
5VT  
Z
TTL  
TTL logic  
TTL-H  
CMOS  
IA  
TTL with hysteresis  
CMOS logic  
Input Analog  
ID  
Input Digital  
OD  
Output Digital  
Output Analog  
I/O Analog  
OA  
IOA  
IOD  
I/O Digital  
GA  
Ground Analog  
Supply Analog  
Supply Digital  
Crystal Oscillator Input  
Crystal Oscillator Output  
Crystal Oscillator Ground  
SA  
SD  
OSCIN  
OSCOUT  
OSCGND  
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 03 – 23 August 2004  
 
3 of 31  
       
PNX2000  
Philips Semiconductors  
Audio video input processor  
Table 3:  
Pins in numerical sequence  
Type  
Pin  
1
Symbol  
Description  
VSSD(I2D)  
GD  
IA  
IA  
IA  
IA  
IA  
IA  
IA  
IA  
IA  
IA  
IA  
IA  
SD  
ID  
IA  
I2D digital ground  
2
DLINK1DP  
DLINK1DN  
DLINK1SP  
DLINK1SN  
DLINK2DP  
DLINK2DN  
DLINK2SP  
DLINK2SN  
DLINK3DP  
DLINK3DN  
DLINK3SP  
DLINK3SN  
VDDD(I2D)  
analog differential data link 1 positive termination  
analog differential data link 1 negative termination  
analog differential strobe link 1 positive termination  
analog differential strobe link 1 negative termination  
analog differential data link 2 positive termination  
analog differential data link 2 negative termination  
analog differential strobe link 2 positive termination  
analog differential strobe link 2 negative termination  
analog differential data link 3 positive termination  
analog differential data link 3 negative termination  
analog differential strobe link 3 positive termination  
analog differential strobe link 3 negative termination  
I2D digital 1.8 V supply voltage  
3
4
5
7
8
9
10  
12  
13  
14  
15  
16  
17  
18  
I2C_ADR  
I2C-bus address select (internal pull-down); TTL; 5VT  
HSYNCFBL1  
horizontal sync (external); fastblanking signal from  
SCART  
19  
20  
HSYNCFBL2  
HVINFO  
IA  
horizontal sync (external); fastblanking signal from  
SCART  
OD  
horizontal and vertical sync information to PNX3000;  
CMOS  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
VSYNC1  
VSYNC2  
VDD3(DTC)  
VDDD(DTC)  
VSS(DTC)  
I2C_SCL  
I2C_SDA  
VSSE  
ID  
ID  
SD  
SD  
GA  
IOD  
IOD  
-
vertical sync (external); TTL; 5VT  
vertical sync (external); TTL; 5VT  
DTC 3.3 V supply voltage  
DTC 1.8 V supply voltage  
DTC analog ground  
I2C-bus clock; TTL; Z; 5VT  
I2C-bus data; TTL; Z; 5VT  
3.3 V ground  
VSS  
-
1.8 V ground  
VDDI  
-
1.8 V supply voltage  
MPIFCLK  
VDDE  
OD  
-
13.5 MHz or 27 MHz to PNX3000; CMOS  
3.3 V supply voltage  
VDDA(PLL)  
-
-
phase locked loop 1.8 V supply voltage  
not connected  
n.c.  
-
VDDI  
1.8 V supply voltage  
VSS  
-
1.8 V ground  
VDDA(XTAL)  
XIN  
OSCVDD 1.8 V crystal oscillator supply voltage  
OSCIN crystal oscillator input  
XOUT  
XGND  
OSCOUT crystal oscillator output  
OSCGND crystal oscillator ground  
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 03 – 23 August 2004  
 
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PNX2000  
Philips Semiconductors  
Audio video input processor  
Table 3:  
Pins in numerical sequence…continued  
Pin  
41  
42  
43  
44  
45  
46  
Symbol  
Type  
Description  
VSSE  
-
3.3 V ground  
VDDI  
-
1.8 V supply voltage  
1.8 V ground  
VSS  
-
VDDM  
-
1.8 V supply voltage for KSFRAMs and KROMs  
external reset input  
RESET_N  
RESET_SEL  
IA  
ID  
selects between using an external reset input or using  
internal POR; TTL; 5VT  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
DCLK  
OD  
OD  
-
reserved; CMOS  
INTOUT  
interrupt line output; Z; 5VT  
3.3 V supply voltage  
VDDE  
LL_CLK  
ID  
reserved; TTL; 5VT  
DVO_CLK  
DVO_VALID  
VDDI  
OD  
OD  
-
digital video output clock; CMOS; Z  
digital video data valid; CMOS; Z  
1.8 V supply voltage  
VSS  
-
1.8 V ground  
DVO_DATA_0  
DVO_DATA_1  
DVO_DATA_2  
DVO_DATA_3  
VSSE  
OD  
OD  
OD  
OD  
-
digital video output state 0; CMOS; Z  
digital video output state 1; CMOS; Z  
digital video output state 2; CMOS; Z  
digital video output state 3; CMOS; Z  
3.3 V ground  
DVO_DATA_4  
DVO_DATA_5  
DVO_DATA_6  
DVO_DATA_7  
DVO_DATA_8  
DVO_DATA_9  
VDDE  
OD  
OD  
OD  
OD  
OD  
OD  
-
digital video output state 4; CMOS; Z  
digital video output state 5; CMOS; Z  
digital video output state 6; CMOS; Z  
digital video output state 7; CMOS; Z  
digital video output state 8; CMOS; Z  
digital video output state 9; CMOS; Z  
3.3 V supply voltage  
VDDI  
-
1.8 V supply voltage  
VSS  
-
1.8 V ground  
I2S_OUT_SD3  
I2S_OUT_SD3_WS  
OD  
OD  
I2S-bus data-out channel 3; CMOS  
I2S-bus word select channel 3; CMOS  
I2S-bus bit clock channel 3; CMOS  
3.3 V ground  
I2S-bus data out channel 6; CMOS  
I2S-bus data out channel 5; CMOS  
I2S-bus data out channel 4; CMOS  
I2S-bus data out channel 2; CMOS  
I2S-bus data out channel 1; CMOS  
I2S-bus system word select; TTL-H; CMOS  
I2S-bus system bit clock; TTL-H; CMOS  
1.8 V supply voltage  
I2S_OUT_SD3_SCK OD  
VSSE  
-
I2S_OUT_SD6  
I2S_OUT_SD5  
I2S_OUT_SD4  
I2S_OUT_SD2  
I2S_OUT_SD1  
I2S_WS_SYS  
I2S_SCK_SYS  
VDDI  
OD  
OD  
OD  
OD  
OD  
IOD  
IOD  
-
9397 750 13928  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 03 – 23 August 2004  
 
5 of 31  
PNX2000  
Philips Semiconductors  
Audio video input processor  
Table 3:  
Pins in numerical sequence…continued  
Pin  
81  
82  
83  
84  
85  
86  
87  
88  
89  
Symbol  
Type  
-
Description  
VSS  
1.8 V ground  
VDDE  
-
3.3 V supply voltage  
I2S_IN_SD6  
I2S_IN_SD5  
I2S_IN_SD4  
I2S_IN_SD3  
I2S_IN_SD2  
I2S_IN_SD1  
ADAC_CLK  
ID  
ID  
ID  
ID  
ID  
ID  
OD  
I2S-bus data in channel 6; TTL; 5VT  
I2S-bus data in channel 5; TTL; 5VT  
I2S-bus data in channel 4; TTL; 5VT  
I2S-bus data in channel 3; TTL; 5VT  
I2S-bus data in channel 2; TTL; 5VT  
I2S-bus data in channel 1; TTL; 5VT  
Used for 128 fs or 256 fs clock output to external audio  
DAC; CMOS.  
90  
-
n.c.  
-
not connected  
91  
VDDE  
3.3 V supply voltage  
92  
TDI  
ID  
OD  
ID  
ID  
ID  
-
JTAG test data in; TTL-H; 5VT  
JTAG test data out; CMOS  
JTAG test clock; TTL-H; 5VT  
JTAG test mode select; TTL-H; 5VT  
JTAG reset (active low); TTL-H; 5VT  
1.8 V supply voltage  
93  
TDO  
94  
TCK  
95  
TMS  
96  
TRST_N  
VDDI  
97  
98  
VSS  
-
1.8 V ground  
99  
VSSE  
-
3.3 V ground  
100  
101  
102  
103  
VSS(ADAC)  
VDDD(ADAC)  
VDDA(ADAC)  
ADAC1_P  
GD  
SD  
SA  
SA  
audio DAC 1.8 V digital ground  
audio DAC 1.8 V digital supply voltage  
audio DAC 3.3 V supply voltage  
Positive analog reference derived via emitter follower  
from PNX3000 V_SND pin.  
104  
105  
ADAC1  
OA  
GA  
analog audio output 1  
ADAC1_N  
Negative analog reference star connected at  
PNX3000.  
106  
ADAC2_N  
GA  
Negative analog reference star connected at  
PNX3000.  
107  
108  
ADAC2  
OA  
SA  
analog audio output 2  
ADAC2_P  
Positive analog reference derived via emitter follower  
from PNX3000 V_SND pin.  
109  
ADAC3_P  
SA  
Positive analog reference derived via emitter follower  
from PNX3000 V_SND pin.  
110  
111  
ADAC3  
OA  
GA  
analog audio output 3  
ADAC3_N  
Negative analog reference star connected at  
PNX3000.  
112  
ADAC4_N  
GA  
Negative analog reference star connected at  
PNX3000.  
113  
114  
ADAC4  
OA  
SA  
analog audio output 4  
ADAC4_P  
Positive analog reference derived via emitter follower  
from PNX3000 V_SND pin.  
9397 750 13928  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 03 – 23 August 2004  
 
6 of 31  
PNX2000  
Philips Semiconductors  
Audio video input processor  
Table 3:  
Pins in numerical sequence…continued  
Pin  
Symbol  
Type  
Description  
115  
ADAC5_P  
SA  
Positive analog reference derived via emitter follower  
from PNX3000 V_SND pin.  
116  
117  
ADAC5  
OA  
GA  
analog audio output 5  
ADAC5_N  
Negative analog reference star connected at  
PNX3000.  
118  
ADAC6_N  
GA  
Negative analog reference star connected at  
PNX3000.  
119  
120  
ADAC6  
OA  
SA  
analog audio output 6  
ADAC6_P  
Positive analog reference derived via emitter follower  
from PNX3000 V_SND pin.  
121  
ADAC7_P  
SA  
Positive analog reference derived via emitter follower  
from PNX3000 V_SND pin.  
122  
123  
ADAC7  
OA  
GA  
analog audio output 7  
ADAC7_N  
Negative analog reference star connected at  
PNX3000.  
124  
ADAC8_N  
GA  
Negative analog reference star connected at  
PNX3000.  
125  
126  
ADAC8  
OA  
SA  
analog audio output 8  
ADAC8_P  
Positive analog reference derived via emitter follower  
from PNX3000 V_SND pin.  
127  
ADAC9_P  
SA  
Positive analog reference derived via emitter follower  
from PNX3000 V_SND pin.  
128  
129  
ADAC9  
OA  
GA  
analog audio output 9  
ADAC9_N  
Negative analog reference star connected at  
PNX3000.  
130  
ADAC10_N  
GA  
Negative analog reference star connected at  
PNX3000.  
131  
132  
ADAC10  
OA  
SA  
analog audio output 10  
ADAC10_P  
Positive analog reference derived via emitter follower  
from PNX3000 V_SND pin.  
133  
ADAC11_P  
SA  
Positive analog reference derived via emitter follower  
from PNX3000 V_SND pin.  
134  
135  
ADAC11  
OA  
GA  
analog audio output 11  
ADAC11_N  
Negative analog reference star connected at  
PNX3000.  
136  
ADAC12_N  
GA  
Negative analog reference star connected at  
PNX3000.  
137  
138  
ADAC12  
OA  
SA  
analog audio output 12  
ADAC12_P  
Positive analog reference derived via emitter follower  
from PNX3000 V_SND pin.  
139  
140  
141  
VSS  
-
-
-
1.8 V ground  
VDDM  
VDDE  
1.8 V supply voltage for KSFRAMs and KROMs  
3.3 V supply voltage  
9397 750 13928  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 03 – 23 August 2004  
 
7 of 31  
PNX2000  
Philips Semiconductors  
Audio video input processor  
Table 3:  
Pins in numerical sequence…continued  
Pin  
142  
143  
144  
Symbol  
Type  
Description  
VSSE  
VDDE  
VSSE  
-
-
-
3.3 V ground  
3.3 V supply voltage  
3.3 V ground  
In the tables that follow, signals of the PNX2000 have been sorted by functional group. For  
quick reference Table 4 identifies each functional group and associated table.  
Table 4:  
Signal groups  
Functional group  
I2D-bus  
Table number  
AUDIO  
I2S-bus  
VIDDEC  
ITU-656  
JTAG  
I2C-bus  
CLOCK  
GTU  
RESET  
DIGITAL SUPPLY  
ANALOG SUPPLY  
Table 5:  
I2D pins  
Pin Type  
Symbol  
Description  
DLINK1DP  
DLINK1DN  
DLINK1SP  
DLINK1SN  
DLINK2DP  
DLINK2DN  
DLINK2SP  
DLINK2SN  
DLINK3DP  
DLINK3DN  
DLINK3SP  
DLINK3SN  
2
IA  
IA  
IA  
IA  
IA  
IA  
IA  
IA  
IA  
IA  
IA  
IA  
analog differential data link 1 positive termination  
analog differential data link 1 negative termination  
analog differential strobe link 1 positive termination  
analog differential strobe link 1 negative termination  
analog differential data link 2 positive termination  
analog differential data link 2 negative termination  
analog differential strobe link 2 positive termination  
analog differential strobe link 2 negative termination  
analog differential data link 3 positive termination  
analog differential data link 3 negative termination  
analog differential strobe link 3 positive termination  
analog differential strobe link 3 negative termination  
3
4
5
7
8
9
10  
12  
13  
14  
15  
Table 6:  
Symbol  
ADAC1  
ADAC2  
ADAC3  
ADAC4  
Audio pins  
Pin Type Description  
104 OA  
analog audio output 1  
analog audio output 2  
analog audio output 3  
analog audio output 4  
107 OA  
110 OA  
113 OA  
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 03 – 23 August 2004  
 
8 of 31  
     
PNX2000  
Philips Semiconductors  
Audio video input processor  
Table 6:  
Symbol  
ADAC5  
Audio pins…continued  
Pin Type Description  
116 OA  
119 OA  
122 OA  
125 OA  
128 OA  
131 OA  
134 OA  
137 OA  
103 SA  
analog audio output 5  
ADAC6  
analog audio output 6  
analog audio output 7  
analog audio output 8  
analog audio output 9  
analog audio output 10  
analog audio output 11  
analog audio output 12  
ADAC7  
ADAC8  
ADAC9  
ADAC10  
ADAC11  
ADAC12  
ADAC1_P  
Positive analog reference derived via emitter follower from  
PNX3000 V_SND pin.  
ADAC1_N  
ADAC2_P  
105 GA  
108 SA  
Negative analog reference star connected at PNX3000.  
Positive analog reference derived via emitter follower from  
PNX3000 V_SND pin.  
ADAC2_N  
ADAC3_P  
106 GA  
109 SA  
Negative analog reference star connected at PNX3000.  
Positive analog reference derived via emitter follower from  
PNX3000 V_SND pin.  
ADAC3_N  
ADAC4_P  
111 GA  
114 SA  
Negative analog reference star connected at PNX3000.  
Positive analog reference derived via emitter follower from  
PNX3000 V_SND pin.  
ADAC4_N  
ADAC5_P  
112 GA  
115 SA  
Negative analog reference star connected at PNX3000.  
Positive analog reference derived via emitter follower from  
PNX3000 V_SND pin.  
ADAC5_N  
ADAC6_P  
117 GA  
120 SA  
Negative analog reference star connected at PNX3000.  
Positive analog reference derived via emitter follower from  
PNX3000 V_SND pin.  
ADAC6_N  
ADAC7_P  
118 GA  
121 SA  
Negative analog reference star connected at PNX3000.  
Positive analog reference derived via emitter follower from  
PNX3000 V_SND pin.  
ADAC7_N  
ADAC8_P  
123 GA  
126 SA  
Negative analog reference star connected at PNX3000.  
Positive analog reference derived via emitter follower from  
PNX3000 V_SND pin.  
ADAC8_N  
ADAC9_P  
124 GA  
127 SA  
Negative analog reference star connected at PNX3000.  
Positive analog reference derived via emitter follower from  
PNX3000 V_SND pin.  
ADAC9_N  
129 GA  
132 SA  
Negative analog reference star connected at PNX3000.  
ADAC10_P  
Positive analog reference derived via emitter follower from  
PNX3000 V_SND pin.  
ADAC10_N  
ADAC11_P  
130 GA  
133 SA  
Negative analog reference star connected at PNX3000.  
Positive analog reference derived via emitter follower from  
PNX3000 V_SND pin.  
ADAC11_N  
ADAC12_P  
135 GA  
138 SA  
Negative analog reference star connected at PNX3000.  
Positive analog reference derived via emitter follower from  
PNX3000 V_SND pin.  
ADAC12_N  
136 GA  
Negative analog reference star connected at PNX3000.  
9397 750 13928  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 03 – 23 August 2004  
 
9 of 31  
PNX2000  
Philips Semiconductors  
Audio video input processor  
Table 7:  
Symbol  
I2S-bus pins  
Pin  
88  
87  
86  
85  
84  
83  
77  
76  
75  
74  
73  
71  
70  
69  
79  
78  
89  
Type Description  
I2S_IN_SD1  
ID  
I2S-bus data in channel 1; TTL; 5VT  
I2S-bus data in channel 2; TTL; 5VT  
I2S_IN_SD2  
ID  
I2S_IN_SD3  
ID  
I2S-bus data in channel 3; TTL; 5VT  
I2S-bus data in channel 4; TTL; 5VT  
I2S-bus data in channel 5; TTL; 5VT  
I2S-bus data in channel 6; TTL; 5VT  
I2S-bus data out channel 1; CMOS  
I2S-bus data out channel 2; CMOS  
I2S-bus data out channel 4; CMOS  
I2S-bus data out channel 5; CMOS  
I2S-bus data out channel 6; CMOS  
I2S-bus bit clock channel 3; CMOS  
I2S-bus word select channel 3; CMOS  
I2S-bus data-out channel 3; CMOS  
I2S-bus system bit clock; TTL-H; CMOS  
I2S-bus system word select; TTL-H; CMOS  
I2S_IN_SD4  
ID  
I2S_IN_SD5  
ID  
I2S_IN_SD6  
ID  
I2S_OUT_SD1  
I2S_OUT_SD2  
I2S_OUT_SD4  
I2S_OUT_SD5  
I2S_OUT_SD6  
I2S_OUT_SD3_SCK  
I2S_OUT_SD3_WS  
I2S_OUT_SD3  
I2S_SCK_SYS  
I2S_WS_SYS  
ADAC_CLK  
OD  
OD  
OD  
OD  
OD  
OD  
OD  
OD  
IOD  
IOD  
OD  
Used for 128 fs or 256 fs clock output to external audio  
DAC; CMOS.  
Table 8:  
VIDDEC pins  
Symbol  
Pin  
20  
18  
19  
21  
22  
Type Description  
HVINFO  
OD  
IA  
horizontal and vertical sync information to PNX3000; CMOS  
HSYNCFBL1  
HSYNCFBL2  
VSYNC1  
horizontal sync (external); fastblanking signal from SCART  
horizontal sync (external); fastblanking signal from SCART  
vertical sync (external); TTL; 5VT  
IA  
ID  
ID  
VSYNC2  
vertical sync (external); TTL; 5VT  
Table 9:  
Symbol  
ITU-656 pins  
Pin Type Description  
DVO_DATA_0 55  
DVO_DATA_1 56  
DVO_DATA_2 57  
DVO_DATA_3 58  
DVO_DATA_4 60  
DVO_DATA_5 61  
DVO_DATA_6 62  
DVO_DATA_7 63  
DVO_DATA_8 64  
DVO_DATA_9 65  
OD  
OD  
OD  
OD  
OD  
OD  
OD  
OD  
OD  
OD  
digital video output state 0; CMOS; Z  
digital video output state 1; CMOS; Z  
digital video output state 2; CMOS; Z  
digital video output state 3; CMOS; Z  
digital video output state 4; CMOS; Z  
digital video output state 5; CMOS; Z  
digital video output state 6; CMOS; Z  
digital video output state 7; CMOS; Z  
digital video output state 8; CMOS; Z  
digital video output state 9; CMOS; Z  
9397 750 13928  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 03 – 23 August 2004  
 
10 of 31  
     
PNX2000  
Philips Semiconductors  
Audio video input processor  
Table 9:  
Symbol  
ITU-656 pins…continued  
Pin  
52  
51  
50  
Type Description  
DVO_VALID  
OD  
OD  
ID  
digital video data valid; CMOS; Z  
DVO_CLK  
LL_CLK  
digital video output clock; CMOS; Z  
reserved; TTL; 5VT [1]  
[1] It is recommended to bias this pad with a 10 kresistor  
Table 10: JTAG pins  
Symbol  
TDO  
Pin  
93  
92  
94  
96  
95  
Type  
OD  
ID  
Description  
JTAG test data out; CMOS  
JTAG test data in; TTL-H; 5VT  
JTAG test clock; TTL-H; 5VT  
JTAG reset (active low); TTL-H; 5VT  
JTAG test mode select; TTL-H; 5VT  
TDI  
TCK  
TRST_N[1]  
ID  
ID  
TMS  
ID  
[1] It is recommended to pull-down TRST_N with a 10 kresistor. This ensures correct reset state of internal  
TAP circuitry and correct POR of the device within defined state machine.  
Table 11: I2C-bus pins  
Symbol  
Pin Type Description  
I2C_SDA  
I2C_SCL  
I2C_ADR  
27  
26  
17  
IOD  
IOD  
ID  
I2C-bus data; TTL; Z; 5VT  
I2C-bus clock; TTL; Z; 5VT  
I2C-bus address select (internal pull-down); TTL; 5VT  
Table 12: Clock pins  
Symbol  
MPIFCLK  
DCLK  
Pin Type  
Description  
31  
47  
38  
39  
40  
OD  
13.5 MHz or 27 MHz to PNX3000; CMOS  
reserved; CMOS  
OD  
XIN  
OSCIN  
crystal oscillator input  
XOUT  
XGND  
OSCOUT crystal oscillator output  
OSCGND crystal oscillator ground  
Table 13: GTU pins  
Symbol  
Pin Type  
Description  
INTOUT  
48  
OD  
interrupt line output; Z; 5VT  
Table 14: Reset pins  
Symbol  
Pin  
Type  
IA  
Description  
RESET_N  
45  
external reset input  
RESET_SEL 46  
ID  
selects between using an external reset input or using  
internal POR; TTL; 5VT  
HIGH = internal reset  
LOW = external reset  
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Table 15: Digital supply pins  
Symbol  
Pin  
Type Description  
VDDE  
32,49,66, 82,91,  
141,143  
-
3.3 V supply voltage  
VSSE  
28,41,59, 72,99,  
142,144  
-
3.3 V ground  
VDDI  
30,35,53,67, 80,97  
-
-
1.8 V supply voltage  
1.8 V ground  
VSS  
29,36,43, 54,68,81,  
98,139  
VDDM  
44,140  
1
-
1.8 V supply voltage for KSFRAMs and KROMs  
I2D digital ground  
I2D digital 1.8 V supply voltage  
audio DAC 1.8 V digital ground  
audio DAC 1.8 V digital supply voltage  
DTC 3.3 V supply voltage  
VSSD(I2D)  
VDDD(I2D)  
VSS(ADAC)  
GD  
SD  
GD  
SD  
SD  
SD  
16  
100  
VDDD(ADAC) 101  
VDD3(DTC)  
VDDD(DTC)  
23  
24  
DTC 1.8 V supply voltage  
[1] VDDI and VDDM can be connected to same 1.8 V supply voltage.  
Table 16: Analog supply pins  
Symbol  
VSSA(I2D)  
VDDA(I2D)  
VDDA(PLL)  
Pin Type  
Description  
I2D analog ground  
I2D analog 1.8 V supply voltage  
phase locked loop 1.8 V supply voltage  
audio DAC 3.3 V supply voltage  
DTC analog ground  
6
GA  
SA  
-
11  
33  
VDDA(ADAC) 102 SA  
VSS(DTC)  
25  
GA  
VDDA(XTAL) 37  
7. Functional description  
7.1 Overview  
OSCVDD  
1.8 V crystal oscillator supply voltage  
Table 17 describes the functions of the hardware blocks (see also PNX2000 Block  
Diagram Figure 1).  
For more detailed functional description refer to the PNX2000 User Manual.  
Table 17: Block function  
Function  
Block  
I2D  
Description  
High speed data link  
Receives data in three streams from PNX3000.  
Video decoder  
processor  
VIDDEC  
Decodes and processes CVBS, YUV or Y/C in YUV  
stream.  
Serial interface  
Global Task Unit  
I2C-bus  
GTU  
To access all the internal registers.  
Generates all the internal clocks, reset and power  
management.  
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Table 17: Block function…continued  
Function  
Block  
Description  
TV sound decoder  
DEMDEC  
DSP  
Demodulation, decoding of terrestrial TV audio standards  
.
Audio processor  
AUDIO DSP Processing analog and digital audio sources.  
Data Capture Unit  
DCU  
Acquires VBI data (Teletext; CC; VPS) and formats in a  
stream.  
Formatter unit  
ITU-656  
BCU  
Formats YUV, VBI data and CVBS data in ITU-656.  
Bus arbitration among all the internal blocks.  
Bus Control Unit  
7.2 Interfaces  
Table 18: Interfaces  
Interface Description  
I2C-bus  
The PNX2000 IC is controlled using an I2C-bus. It performs like an I2C-bus to PI-bus  
bridge, i.e. translates I2C-bus slave received commands to PI-bus master commands.  
I2D  
Receives data in three streams from PNX3000.  
I2S-bus  
Serial digital audio interface (6 stereo inputs, 6 stereo outputs) for connection to other  
devices that support the I2S-bus standard. Can be used to receive decoded sound  
from a multi-channel digital audio decoder, provide additional ADCs and DACs, or loop  
audio signals through an external processor or delay line.  
ITU-656  
DACS  
Mainly intended to transfer output data stream externally to the PNX8550, but the  
output data stream could also be readable by other ITU-656 input devices that  
implement data valid signalling.  
Digital-analog converters used to generate analog outputs from Sound Core.  
7.3 Features in detail  
7.3.1 Video  
Automatic Gain Control (AGC) to correct amplitude errors at input source.  
Synchronization identification (used for channel search).  
Sync processing for 1fH and 2fH video input source.  
Standard detection of PAL, NTSC or SECAM and various 1fH and 2fH component  
video input sources.  
1fH video  
Color decoding (ITU-601) for PAL, NTSC or SECAM input sources.  
2D comb filtering.  
Support for component video sources with sync on CVBS or green.  
Fastblank insertion of RGB signals onto CVBS input.  
2fH video  
Support for various progressive and interlaced component video sources.  
Synchronization of video sources with sync on Y or external H/V inputs.  
VBI data capture  
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Audio video input processor  
Decoding of 525 line standards; WST, WSS, VPS, CC, VITC.  
Decoding of 625 line standards; WST, WSS, CC, VITC.  
ITU-656 output interface  
Video and VBI formatting into ITU-style output data stream, compliant to  
ITU-656/1364 (exception being the use of a data valid signal).  
Interfacing to PNX8550 IC.  
Support for CVBS/C mode to interface to external picture improvement devices.  
7.3.2 Audio  
Demodulator and decoder  
Demodulator and Decoder Easy Programming (DDEP).  
Auto Standard Detection (ASD).  
Static Standard Selection (SSS).  
DQPSK demodulation for different standards, simultaneously with 1-channel FM  
demodulation.  
NICAM decoding (B/G, I, D/K and L standard).  
Two-carrier multi-standard FM demodulation (B/G, D/K and M standard).  
Decoding for three analog multi-channel systems (A2, A2+ and A2*) and satellite  
sound.  
Adaptive de-emphasis for satellite FM.  
Optional AM demodulation for system L, simultaneously with NICAM.  
Identification A2 systems (B/G, D/K and M standard) with different identification time  
constants.  
FM pilot carrier present detector.  
Monitor selection for FM/AM DC values and signals, with peak and quasi peak  
detection option.  
BTSC MPX decoding.  
SAP decoding.  
dbx® 3 TV noise reduction.  
Japan (EIAJ) decoding.  
FM radio decoding.  
Soft muting for DEMDEC outputs DEC, MONO and SAP.  
FM over modulation adaptation option to avoid clipping and distortion.  
Sample Rate Conversion (SRC) for up to three demodulated terrestrial audio signals.  
Allows processing of SCART and demodulated terrestrial signals.  
Audio multi-channel decoder  
Dolby Pro Logic II™  
3. dbx is a registered trademark of Carillon Electronics Corp.  
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Audio video input processor  
6-channel processing for Main Left and Main Right, Subwoofer, Center, Surround Left  
and Surround Right.  
Volume and tone control  
Automatic Volume Level (AVL) control.  
Smooth volume control.  
Master volume control and balance.  
Soft mute.  
Loudness.  
Bass, treble.  
Dynamic Bass Enhancement (DBE).  
Dynamic ULTRABASS (DUB).  
Non-processed subwoofer.  
5-band equalizer.  
Acoustical compensation.  
Programmable beeper.  
Noise generation for loudspeaker level trimming.  
Reflection and delay  
Dolby Pro Logic II™ delay.  
Pseudo hall/matrix function.  
Psychoacoustic spatial algorithms, downmix and split  
Incredible Mono.  
Incredible Stereo.  
Virtual Dolby Surround™.  
Virtual Dolby Digital™.  
Bass Redirection according to Dolby™ specifications.  
BBE® Sound Processing 4  
Interfaces and switching  
Digital audio input interface (stereo I2S-bus input interface).  
Digital audio output interface (stereo I2S-bus output interface).  
Digital crossbar switch for all digital signal sources and destinations.  
Output crossbar for exchange of channel processing functionality.  
Voice recognition output interface (stereo I2S-bus output interface).  
Audio monitoring for level detection.  
Eight audio DACs for 6-channel loudspeaker outputs and stereo headphones output.  
Four audio DACs for stereo SCART output and stereo LINE output.  
4. BBE is a registered trademark of BBE Sound Inc. See Section 18.  
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Audio video input processor  
Serial data link interfacing for analog multi-purpose interface PNX3000.  
8. Television application  
Figure 3 shows an overview of the top level hardware architecture of a TV application,  
using the PNX3000 and PNX2000 as an analog front-end and the PNX8550 as the main  
processor. This system is aimed at the hybrid (analog or digital) TV market.  
The main SOC in the system, PNX8550, performs key features for high quality television  
like video quality enhancement, motion compensation and picture-in-picture processing.  
PNX2000 together with PNX3000 are used to perform the input decoding of a single  
stream of analog audio and a single stream of analog video (1fH or 2fH) broadcast signals.  
PNX2000 performs the following main functions:  
Color decoding into ITU-601 compatible format (1fH or 2fH).  
A digital interface to external 3D comb filter.  
VBI data capture (Teletext, WSS, CC).  
ITU-656 formatting for communication to PNX8550.  
Audio demodulation and decoding.  
Audio processing and D-A conversion.  
The audio data is transferred between PNX2000 and PNX8550 using I2S-bus. PNX2000  
and PNX3000 are controlled from PNX8550 via the I2C-bus.  
CVBS  
RGB  
10 bits (3×)  
SIF  
VIF  
YUV (656)  
TUNERS  
UV1316  
UV13361  
RGB  
AMPLIFIER  
2
2
I D  
audio I S-bus  
SCART  
DISPLAY  
PROCESSOR  
2
audio I S-bus  
PNX2000  
PNX8550  
21  
20  
18  
20  
L/R  
audio  
(2×)  
21  
19  
17  
DEFL.  
CONT.  
CVBS Y/C  
2
audio I S-bus  
16  
14  
12  
10  
8
18  
16  
15  
14  
12  
RGB 2  
L/R audio 2  
CVBS 1  
(3×)  
PNX3000  
13  
11  
9
10  
8
32-bit  
DDR  
16 Mb  
6
7
4
6
L/R audio 1  
5
2
4
3
2
1
FLASH  
ROM  
8-bit or 16-bit  
18 Mb  
status  
LEVEL ADJUSTMENT  
AUDIO  
AMPLIFIER  
STANDBY  
MICRO-  
REMOTE CONTROL  
CONTROLLER  
mce558  
LOCAL KEYPAD  
Fig 3. TV application  
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9. Limiting values  
Permanent damage may occur if absolute maximum ratings are exceeded. Prolonged  
operation at maximum rating may significantly reduce the reliability of the product.  
Table 19: Absolute maximum ratings  
Ratings are valid only within operating temperature range unless otherwise specified. All voltages are with respect to VSS  
unless otherwise stated.  
Symbol  
VDD(core)  
VDD(I/O)  
VI  
Parameter  
Min  
0.5  
0.5  
0.5  
0.5  
100  
-
Max  
Unit  
V
supply voltage  
+2.5  
supply voltage  
DC input voltage ( [1] [2] and  
+4.6  
V
)
VDD(I/O) + 0.5  
V
VI  
DC input voltage 5V tolerant I/O pins ( [2] and [3]  
latch-up current ( [4]  
electrostatic discharge voltage HBM ( [5] and  
electrostatic discharge voltage MM ( [6] and[7]  
storage temperature  
)
)
+6  
V
Ilatchup  
Vesd  
)
-
mA  
kV  
V
±2  
Vesd  
)
-
±200  
+125  
Tstg  
40  
°C  
[1] Not to exceed 4.6 V.  
[2] Including voltage on outputs in 3-state mode.  
[3] Only valid when the VDD(I/O) supply voltage is present.  
[4] Valid for : (0.5 × VDD) < V < +(1.5 × VDD); Tj < 125 °C.  
[5] Human Body Model, Ileak < 1 mA.  
[6] Machine Model 0.5 mH, Ileak < 1 mA.  
[7] This product includes circuits specifically designed for the protection of its internal devices from the damaging effects of excessive static  
charge. However, it is suggested that conventional precautions be taken to avoid applying voltages greater than the rated maximum.  
10. Characteristics  
10.1 Static characteristics  
Table 20: Static characteristics: power supply pins  
Tamb = 0 °C to +70 °C to commercial unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
1.8V Power Supply Pins: VDDI, VDDM, VDDD(I2D), VDDA(I2D), VDDA(PLL), VDDA(XTAL), VDDD(ADAC), VDDD(DTC)  
VDD(core)  
IDD(core)  
supply voltage, 1.8 V supplies  
supply current, 1.8 V supplies  
-
1.65  
-
1.8  
1.95  
-
V
VDD(core) = 1.8 V  
250  
mA  
3.3V Power Supply Pins: VDDE, VDD3(DTC), VDDA(ADAC)  
VDD(3V3)  
IDD(3V3)  
supply voltage, 3.3 V supplies  
supply current, 3.3 V supplies  
-
3.0  
-
3.3  
50  
3.6  
-
V
VDD(core) = 3.3 V  
mA  
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Audio video input processor  
Table 21: Static characteristics: digital pins  
Tamb = 0 °C to +70 °C to commercial unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min Typ Max  
Unit  
I2S inputs: I2S_IN_SD1-6, I2C Address: I2C_ADR  
IIL  
LOW-level input current  
input voltage  
Vi = 0  
-
-
1
µA  
V
VI  
-
0
-
5.5  
-
VIH  
VIL  
IPD  
HIGH-level input voltage  
LOW-level input voltage  
pull-down current  
-
2.0  
-
-
V
-
-
0.8  
75  
V
Vi = VDD(I/O)  
20  
50  
µA  
External Sync: VSYNC1, VSYNC2, Reset: RESET_SEL, ITU-656: LL_CLK  
IIL  
LOW-level input current  
HIGH-level input current  
input voltage  
Vi = 0  
-
-
-
-
-
-
1
µA  
µA  
V
IIH  
VI  
Vi = VDD(I/O)  
-
1
-
-
-
0
5.5  
-
VIH  
VIL  
HIGH-level input voltage  
LOW-level input voltage  
2.0  
-
V
0.8  
V
Jtag inputs: TDI, TCK, TRST_N, TMS  
IIH  
HIGH-level input current  
input voltage  
Vi = VDD(I/O)  
-
-
1
µA  
V
VI  
-
0
-
5.5  
-
VIH  
VIL  
Vhys  
IPU  
HIGH-level input voltage  
LOW-level input voltage  
hysteresis voltage  
pull-up current  
-
2.0  
-
V
-
-
-
-
0.8  
-
V
-
0.3  
V
Vi = 0  
25 50 65  
µA  
µA  
VDD(I/O) < Vi < 5 V  
0
0
0
I2C Pins: I2C_SDA, I2C_SCL  
CI  
input capacitance  
-
-
5
-
pF  
µA  
µA  
V
ILI  
input leakage current [1]  
max. input current [2]  
input voltage  
VDD(3V3) = 3.3 V; Tamb = 25 °C  
1.37 1.85 2.45  
8.20 10.7 12.45  
IIN(MAX)  
VI  
at 5 V  
-
0
-
5
VIL  
LOW-level input voltage  
HIGH-level input voltage  
LOW-level output voltage  
LOW-level output current  
-
-
-
0.8  
-
V
VIH  
VOL  
IOL  
-
2.0  
-
V
-
-
-
-
0.4  
-
V
VOL=0.4V  
8.45  
mA  
ITU-656 Outputs: DVO_DATA_0-9, DVO_VALID, DVO_CLK  
Ioz  
3-state output leakage  
VO = 0  
-
-
1
µA  
VO = VDD(I/O)  
VI  
input voltage  
-
0
-
-
-
-
-
-
-
5.5  
-
V
VOH  
VOL  
IOH  
IOL  
IOH  
IOL  
HIGH-level output voltage  
LOW-level output voltage  
HIGH-level output current  
LOW-level output current  
HIGH-level short circuit current  
LOW-level short circuit current  
IOH = 4 mA  
IOL = 4 mA  
VOH = 2.4  
VOL = 0.4 V  
VOH = 0  
2.4  
-
V
0.4  
-
V
4  
4
mA  
mA  
mA  
mA  
-
-
45  
50  
VOL = VDD(I/O)  
-
I2S I/O: I2S_SCK_SYS, I2S_WS_SYS  
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Audio video input processor  
Table 21: Static characteristics: digital pins…continued  
Tamb = 0 °C to +70 °C to commercial unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min Typ Max  
Unit  
IIL  
LOW-level input current  
HIGH-level input current  
input voltage  
Vi = 0  
-
-
1
µA  
µA  
V
IIH  
Vi = VDD(I/O)  
-
-
1
VI  
-
-
-
-
0
-
VDD(I/O)  
VIH  
VIL  
Vhys  
Ioz  
HIGH-level input voltage  
LOW-level input voltage  
hysteresis voltage  
2.0  
-
-
V
-
-
-
-
0.8  
-
V
0.4  
-
V
3-state output leakage  
VO = 0  
1
µA  
VO = VDD(I/O)  
VOH  
VOL  
IOH  
IOL  
HIGH-level output voltage  
LOW-level output voltage  
HIGH-level output current  
LOW-level output current  
HIGH-level short circuit current  
LOW-level short circuit current  
IOH = 8 mA  
IOL = 8 mA  
VOH = 2.4  
2.4  
-
-
-
-
-
-
-
-
V
0.4  
-
V
8  
8
mA  
mA  
mA  
mA  
VOL = 0.4 V  
VOH = 0  
-
IOH  
-
95  
95  
IOL  
VOL = VDD(I/O)  
-
I2S Outputs: I2S_OUT_SD1-6, JTAG Output: TDO, PNX3000 Clock: MPIFCLK, Sync Output: HVINFO  
VOH  
VOL  
IOH  
IOL  
HIGH-level output voltage  
LOW-level output voltage  
HIGH-level output current  
LOW-level output current  
HIGH-level short circuit current  
LOW-level short circuit current  
IOH = 4 mA  
IOL = 4 mA  
VOH = 2.4  
2.4  
-
-
-
-
-
-
-
-
V
0.4  
-
V
4  
4
mA  
mA  
mA  
mA  
VOL = 0.4V  
VOH = 0  
-
IOH  
-
45  
50  
IOL  
VOL = VDD(I/O)  
-
I2S Output: I2S_OUT_SD3_SCK, I2S_OUT_SD3_WS, ADAC_CLK, Clock Output: DCLK  
VOH  
VOL  
IOH  
IOL  
HIGH-level output voltage  
LOW-level output voltage  
HIGH-level output current  
LOW-level output current  
HIGH-level short circuit current  
LOW-level short circuit current  
IOH = 8 mA  
IOL = 8 mA  
VOH = 2.4  
2.4  
-
-
-
-
-
-
-
-
V
0.4  
-
V
8  
8
mA  
mA  
mA  
mA  
VOL = 0.4 V  
VOH = 0  
-
IOH  
IOL  
Interrupt: INTOUT  
-
95  
95  
VOL = VDD(I/O)  
-
Ioz  
3-state output leakage  
VO = 0  
-
-
1
µA  
VO = VDD(I/O)  
VI  
input voltage  
-
0
-
-
-
-
-
5.5  
0.4  
-
V
VOL  
IOL  
IOL  
LOW-level output voltage  
LOW-level output current  
LOW-level short circuit current  
IOL = 8 mA  
VOL = 0.4 V  
VOL = VDD(I/O)  
V
8
-
mA  
mA  
140  
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Audio video input processor  
Table 22: Static characteristics: analog pins  
Tamb = 0 °C to +70 °C to commercial unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max Unit  
External Sync: HSYNCFBL1, HSYNCFBL2  
VIT  
VIT  
input threshold  
input threshold  
dtc_lowth = 0  
dtc_lowth = 1  
-
-
1.65  
0.65  
-
-
V
V
Reset: RESET_N  
Vtrip_high high trip level  
Vtrip_low low trip level  
RESET_SEL = 0  
RESET_SEL = 0  
1.0  
1.2  
1.4  
1.3  
V
V
0.95 1.1  
I2D Inputs: DLINK1-3DP, DLINK1-3DN,DLINK1-3SP, DLINK1-3SN  
Vsens  
input sensitivity  
-
-
6
-
mV  
Zdiff  
differential line load impedance  
data pos. range  
across input diff pair  
-
100  
-
VDATA(pos)  
VDATA(neg)  
VSTROBE(pos)  
VSTROBE(neg)  
-
-
-
-
0
0
0
0
-
-
-
-
300  
300  
300  
300  
mV  
mV  
mV  
mV  
data neg. range  
strobe pos. range  
strobe neg. range  
Audio DACs: ADAC1-12P, ADAC1-12N  
VREFP  
VREFN  
IREFP  
positive reference voltage  
negative reference voltage  
positive reference current  
-
-
-
3.0  
3.3  
0
3.6  
V
-
-
-
-
V
820  
µA  
Audio DACs: ADAC1-12  
VOUT(rms)  
output voltage (rms); single-ended, digital  
-
-
1.17  
-
V
i/p level = 0 dBFS  
output resistance  
load resistance  
ROUT  
RL  
-
-
0.7  
10  
1.0  
-
1.3  
-
kΩ  
kΩ  
10.2 Dynamic characteristics  
Table 23: Dynamic characteristics  
Symbol  
I2C  
Parameter  
Conditions  
Min Typ  
Max  
Unit  
fclk  
clock frequency  
-
-
400  
550  
-
kHz  
tr  
tf  
rise time  
fall time  
1.5 kext. pull-up; 160 pF load  
-
-
ns  
ns  
1.5 kext. pull-up; 160 pF load  
130 162  
245  
Viddec: HVINFO (slew rate limited)  
tthl  
output transition time (H to L)  
output transition time (L to H)  
30 pF load  
30 pF load  
-
-
10  
10  
13.8  
13.8  
ns  
ns  
ttlh  
ITU-656  
tsu(DATA)  
data setup at Rx  
40 pF load  
-
-
7.3  
ns  
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Table 23: Dynamic characteristics…continued  
Symbol  
th(DATA)  
I2S  
Parameter  
Conditions  
Min Typ  
Max  
Unit  
data hold at Rx  
40 pF load  
-
-
4.9  
ns  
fs  
audio sample frequency  
SCK frequency  
-
32  
-
48  
48  
-
kHz  
-
fSCK  
I2S-bus master mode  
I2S-bus slave mode  
I2S-bus master mode  
I2S-bus slave mode  
I2S-bus master mode; Cload = 30 pF  
64fs  
fSCK  
SCK frequency  
32fs 64fs  
256fs  
60  
65  
5
-
DFSCK  
DFSCK  
tRSCK  
tRSCK  
td  
SCK duty factor  
40  
35  
-
50  
%
SCK duty factor  
-
%
SCK rise / fall time  
SCK rise / fall time  
-
ns  
ns  
TSCK  
I2S-bus slave mode; fSCK = 3.072 MHz -  
TSCK = 1/fSCK 0.3  
-
50  
0.7  
delay time: SCK to WS and SD  
outputs [2]  
0.5  
th  
ts  
hold time: SCK to WS and SD inputs -  
0
-
-
-
-
ns  
setup time: WS and SD inputs to  
SCK  
TSCK = 1/fSCK  
0.2  
TSCK  
I2D  
fclock(WORD) word clock frequency  
-
-
-
-
-
-
-
-
13.5  
44  
-
-
-
-
MHz  
bit  
WL  
word length  
data rate  
DR  
594  
297  
Mbit/s  
MHz  
fclock(BIT)  
bit clock freq.  
JTAG Clock Reset  
tlow  
Time RESET_N should be below  
Vtrip_high before internal reset = 1.  
RESET_SEL = 0  
RESET_SEL = 0  
-
-
-
-
11  
2
µs  
thigh  
Time RESET_N should be above  
Vtrip_high before internal reset = 0  
(after tpulse).  
µs  
tpulse  
Time before PNX2000 internal reset RESET_SEL = 0  
= 0 [3]  
200  
-
-
ns  
.
[1] Allowed SCK/WS ratios are 32, 48, 64, 128 and 256 SCK periods per WS period.  
[2] All timings relative to the rising edge of SCK.  
[3] See Section 10.4 for waveforms.  
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10.3 Audio DAC characteristics  
Table 24: Dynamic characteristics: Audio DAC  
Tamb = 0 °C to +70 °C for commercial unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min Typ  
Max Unit  
Audio DAC Outputs: ADAC1-12  
fs  
audio sample frequency  
-
32  
-
94  
48  
-
kHz  
dB  
S/N  
Signal to Noise Ratio, CCIR-2 k  
weighted  
outputs muted; reference f = 2 kHz,  
0 dBFS  
(THD+N)/S Total Harmonic Distortion + Noise to f =1 kHz; 0 dBFS; 22 kHz  
-
77  
-
dB  
Signal ratio  
measurement bandwidth  
fres  
frequency response  
+/-1 dB  
<10  
-
-
22.5 kHz  
- dB  
αct  
crosstalk between adjacent DACs  
f = 1 kHz; 0 dBFS  
90  
[1] Allowed audio sample frequencies are 32 kHz, 44.1 kHz and 48 kHz. Default fS in I2S-bus master mode is 48 kHz.  
The audio DACs are based on a switched-resistor architecture which acts as a controlled  
voltage divider between the positive and negative references ADACn_P and ADACn_N.  
Therefore all noise on the reference pins will spread directly to the associated output pin  
ADACn. Consequently it is important to provide adequate filtering of the reference voltage  
to allow optimum signal-to-noise performance. Also, the voltage difference between  
ADACn_P and SDAC_3V3 should be kept to a minimum as any difference will degrade  
distortion performance.  
The DACs have an internal resolution of 4 bits, running at a clock frequency of 128 fS,  
using a noise shaper circuit to shift the quantization noise to out-of-band frequencies. To  
prevent HF overloading of the circuit that is driven by the DAC outputs, a 3.3 nF capacitor  
should be used to filter off the HF signal content. Together with the DAC’s nominal output  
impedance of 1 k, a first order roll-off at approximately 50 kHz will result. One capacitor  
is required for each DAC output, connected between ADACn and the corresponding  
ADACn_N.  
10.4 Timing  
10.4.1 Clock  
Crystal specification  
The crystal oscillator can be used with an external crystal, or in bypass mode with external  
clock signal, see Figure 4.  
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V
DDA  
V
SSA  
V
V
SSA  
pd  
xtm  
pd  
xtm  
DDA  
XO  
XO  
clkout  
clkout  
on-chip  
off-chip  
osc_in  
osc_out  
osc_in  
osc_out  
n.c.  
clock  
(a)  
(b)  
Cx1  
Cx2  
mce560  
Fig 4. Application diagram: (a) slave/test mode, (b) oscillation mode  
The supported crystal/external clock frequencies are 27 MHz and 13.5 MHz. The crystal  
oscillator is followed by a selectable divide-by-two frequency divider giving three available  
clock frequencies, as shown in Table 25.  
Table 25: Primary clock settings  
Clock/Crystal Input  
27 MHz  
Divider setting  
Clock frequency  
27 MHz  
x/1  
x/2  
x/1  
x/2  
27 MHz  
13.5 MHz  
13.5 MHz  
13.5 MHz  
13.5 MHz  
6.75 MHz  
The crystal specification is:  
Package: surface mount.  
Accuracy: (±50 ppm).  
Temperature: (±50 ppm).  
Operating temperature range: 20 to +70 oC.  
Load capacitance: 30 pF.  
Table 26: Crystal parameters  
Oscillator  
Crystal load  
Max.crystal series  
resistance (RS)  
External load  
frequency (fc)  
13.5 MHz  
capacitance (CL)  
capacitors (Cx1; Cx2)  
10 pF  
20 pF  
30 pF  
< 600 Ω  
< 255 Ω  
< 140 Ω  
2 x 18 pF  
2 x 38 pF  
2 x 58 pF  
27 MHz  
10 pF  
20 pF  
30 pF  
< 130 Ω  
< 50 Ω  
n.a.  
2 x 18 pF  
38 pF; 18 pF  
n.a.  
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10.4.2 Reset  
Audio video input processor  
long external reset  
produces internal reset  
short spike  
ignored  
RESET_N  
t
t
pulse  
low  
internal  
reset  
t
high  
mce561  
RESET_N pin and internal reset timing  
Fig 5. PNX2000 reset  
10.4.3 ITU-656  
DVO_CLK  
DVO_DATA[9:0]  
DVO_VALID  
mce562  
t
t
h(DATA)  
su(DATA)  
Fig 6. Timing ITU interface  
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Audio video input processor  
11. Glossary  
AGC................. Automatic Gain Control  
ASD................. Auto Standard Detection  
AVL.................. Auto Volume Level  
SSOP...............Shrink Small Outline Package  
SOC.................System On Chip  
VBI...................Vertical Blanking Interval  
VIDDEC ...........Video front-end Decoder  
VITC.................Vertical Interval Time Code  
VPS..................Video Program System  
WSS.................Wide Screen Signaling  
WST.................World System Teletext  
BCU................. Bus Control Unit  
BTSC............... Broadcast TV System Committee  
DBE................. Dynamic Base Enhancement  
DCU................. Data Capture Unit  
DDEP ..............Demodulator and Decoder Easy  
Programming  
DEMDEC......... Demodulator Decoder  
DQPSK............ Differential Quadrature Phase Shift Keying  
DSP ................. Digital Signal Processor  
DUB................. Dynamic UltraBass  
DVD ................. Digital Video Disc  
EIAJ ................ Electronic Industries Association of Japan  
GTU................. Global Task Unit  
HBM ................ Human Body Model  
LQFP............... Low profile Quad Flat Package  
MM .................. Machine Model  
MPX................. Multiplexer  
NICAM............. Near Instantaneous Compounded Audio  
Multiplex  
NTSC............... National TV Systems Committee  
PAL.................. Phase Alternate Line  
SAP ................. Secondary Audio Program  
SCART ............ Syndicate for Constructors of Apparatus for  
Radio and Television  
SECAM ........... Sequential Color and Memory  
SMD ................ Surface Mount Device  
SRC................. Sample Rate Conversion  
SSS ................. Static Standard Selection  
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Audio video input processor  
12. Package outline  
LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm  
SOT486-1  
y
X
A
108  
109  
73  
72  
Z
E
e
H
A
E
2
A
E
(A )  
3
A
1
θ
w M  
p
L
p
b
L
pin 1 index  
detail X  
37  
144  
1
36  
v M  
Z
A
w M  
D
b
p
e
D
B
H
v M  
B
D
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
E
e
H
D
H
E
L
L
p
v
w
y
Z
Z
θ
1
2
3
p
D
E
max.  
7o  
0o  
0.15 1.45  
0.05 1.35  
0.27 0.20 20.1 20.1  
0.17 0.09 19.9 19.9  
22.15 22.15  
21.85 21.85  
0.75  
0.45  
1.4  
1.1  
1.4  
1.1  
mm  
1.6  
0.25  
1
0.2 0.08 0.08  
0.5  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
00-03-14  
03-02-20  
SOT486-1  
136E23  
MS-026  
Fig 7. LQFP package outline  
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13. Soldering  
13.1 Introduction to soldering surface mount packages  
This text gives a very brief insight to a complex technology. A more in-depth account of  
soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages  
(document order number 9398 652 90011).  
There is no soldering method that is ideal for all IC packages. Wave soldering can still be  
used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these  
situations reflow soldering is recommended. In these situations reflow soldering is  
recommended.  
13.2 Reflow soldering  
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and  
binding agent) to be applied to the printed-circuit board by screen printing, stencilling or  
pressure-syringe dispensing before package placement. Driven by legislation and  
environmental forces the worldwide use of lead-free solder pastes is increasing.  
Several methods exist for reflowing; for example, convection or convection/infrared  
heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)  
vary between 100 and 200 seconds depending on heating method.  
Typical reflow peak temperatures range from 215 to 270 °C depending on solder paste  
material. The top-surface temperature of the packages should preferably be kept:  
below 220 °C (SnPb process) or below 245 °C (Pb-free process)  
for all BGA and SSOP-T packages  
for packages with a thickness 2.5 mm  
for packages with a thickness < 2.5 mm and a volume 350 mm3 so called  
thick/large packages.  
below 235 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a  
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.  
Moisture sensitivity precautions, as indicated on packing, must be respected at all times.  
13.3 Wave soldering  
Conventional single wave soldering is not recommended for surface mount devices  
(SMDs) or printed-circuit boards with a high component density, as solder bridging and  
non-wetting can present major problems.  
To overcome these problems the double-wave soldering method was specifically  
developed.  
If wave soldering is used the following conditions must be observed for optimal results:  
Use a double-wave soldering method comprising a turbulent wave with high upward  
pressure followed by a smooth laminar wave.  
For packages with leads on two sides and a pitch (e):  
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larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be  
parallel to the transport direction of the printed-circuit board;  
smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the  
transport direction of the printed-circuit board.  
The footprint must incorporate solder thieves at the downstream end.  
For packages with leads on four sides, the footprint must be placed at a 45° angle to  
the transport direction of the printed-circuit board. The footprint must incorporate  
solder thieves downstream and at the side corners.  
During placement and before soldering, the package must be fixed with a droplet of  
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe  
dispensing. The package can be soldered after the adhesive is cured.  
Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or  
265 °C, depending on solder material applied, SnPb or Pb-free respectively.  
A mildly-activated flux will eliminate the need for removal of corrosive residues in most  
applications.  
13.4 Manual soldering  
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage  
(24 V or less) soldering iron applied to the flat part of the lead. Contact time must be  
limited to 10 seconds at up to 300 °C.  
When using a dedicated tool, all other leads can be soldered in one operation within  
2 to 5 seconds between 270 and 320 °C.  
13.5 Package related soldering information  
Table 27: Suitability of surface mount IC packages for wave and reflow soldering methods  
Package [1]  
Soldering method  
Wave  
Reflow [2]  
BGA, LBGA, LFBGA, SQFP, SSOP-T[3], TFBGA, not suitable  
VFBGA  
suitable  
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, not suitable [4]  
HTQFP, HTSSOP, HVQFN, HVSON, SMS  
suitable  
PLCC[5], SO, SOJ  
LQFP, QFP, TQFP  
SSOP, TSSOP, VSO, VSSOP  
PMFP [8]  
suitable  
suitable  
not recommended[5] [6]  
not recommended[7]  
not suitable  
suitable  
suitable  
not suitable  
[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026);  
order a copy from your Philips Semiconductors sales office.  
[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the  
maximum temperature (with respect to time) and body size of the package, there is a risk that internal or  
external package cracks may occur due to vaporization of the moisture in them (the so called popcorn  
effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit  
Packages; Section: Packing Methods.  
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[3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no  
account be processed through more than one soldering cycle or subjected to infrared reflow soldering with  
peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package  
body peak temperature must be kept as low as possible.  
[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the  
solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink  
on the top side, the solder might be deposited on the heatsink surface.  
[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave  
direction. The package footprint must incorporate solder thieves downstream and at the side corners.  
[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is  
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.  
[7] Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm;  
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.  
[8] Hot bar or manual soldering is suitable for PMFP packages.  
14. Revision history  
Table 28: Revision history  
Rev Date  
CPCN  
Description  
03 20040823  
02 20040712  
01 20040504  
Minor revision (9397 750 13928)  
Upgraded to Product data (9397 750 13591). Table 3 and Table 4 added.  
Preliminary data (9397 750 12066)  
9397 750 13928  
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15. Data sheet status  
Level  
Data sheet  
status [1]  
Product  
status [2] [3]  
Definition  
I
Objective data  
Development  
This data sheet contains data from the objective specification for product development. Philips Semiconductors  
reserves the right to change the specification in any manner without notice.  
II  
Preliminary data Qualification  
This data sheet contains data from the preliminary specification. Supplementary data will be published at a later  
date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the  
design and supply the best possible product.  
III  
Product data  
Production  
This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make  
changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be  
communicated via a Customer Product/Process Change Notification (CPCN).  
[1]  
[2]  
Consult the most recently issued data sheet before initiating or completing a design.  
products, and makes no representations or warranties that these products are  
free from patent, copyright, or mask work right infringement, unless otherwise  
specified.  
The product status of the device(s) described in this data sheet may have changed  
since this data sheet was published. The latest information is available on the  
[3]  
For data sheets describing multiple type numbers, the highest-level product status  
determines the data sheet status  
18. Licenses  
16. Definitions  
Purchase of Philips I2C components  
Purchase of Philips I2C components conveys a license  
under the Philips’ I2C patent to use the components in the  
I2C system provided the system conforms to the I2C  
specification defined by Philips. This specification can be  
ordered using the code 9398 393 40011.  
Short-form specification – The data in a short-form specification is  
extracted from a full data sheet with the same type number and title. For  
detailed information see the relevant data sheet or data handbook.  
Limiting values definition – Limiting values given are in accordance with  
the Absolute Maximum Rating System (IEC 60134). Stress above one or  
more of the limiting values may cause permanent damage to the device.  
These are stress ratings only and operation of the device at these or at any  
other conditions above those given in the Characteristics sections of the  
specification is not implied. Exposure to limiting values for extended periods  
may affect device reliability.  
Dolby Laboratories  
‘Dolby’ and ‘Pro Logic’ are trademarks of Dolby Laboratories, San  
Francisco, USA. Products are available to licensees of Dolby Laboratories  
Licensing Corp., 100 Potrero Avenue, San Francisco, CA, 94103, USA. Tel:  
1-415-558-0200, Fax: 1-415-863-1373.  
Application information – Applications that are described herein for any of  
these products are for illustrative purposes only. Philips Semiconductors  
make no representation or warranty that such applications will be suitable for  
the specified use without further testing or modification.  
Supply of this implementation of Dolby Technology does not convey a  
license, nor imply a right under any patent to use this implementation in any  
final product. A license for such use is required from Dolby Laboratories.  
BBE Sound  
BBE is a registered trademark of BBE Sound Inc., 5381 Production Drive,  
Huntington Beach, CA, 92649, USA. The use of BBE needs licensing from  
BBE Sound Inc. Tel: 1-714-897-6766, Fax: 1-714-895-6728.  
17. Disclaimers  
Life support – These products are not designed for use in life support  
appliances, devices, or systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips Semiconductors  
customers using or selling these products for use in such applications do so  
at their own risk and agree to fully indemnify Philips Semiconductors for any  
damages resulting from such application.  
dbx - TV noise reduction  
A Set-Maker License is required for use of this product under one (or more)  
of the following patents: US4,539,526; 5,796,842; 6,118,879 and U.S.  
Patent Application 09/638245 . For further information contact THAT  
Corporation, 45 Sumner Street, Milford, Massachusetts 01757-1656, USA.  
Tel: 1-508-478-9200, FAX: 1-508-478-0990  
Right to make changes – Philips Semiconductors reserves the right to  
make changes in the products - including circuits, standard cells, and/or  
software - described or contained herein in order to improve design and/or  
performance. When the product is in full production (status ‘Production’),  
relevant changes will be communicated via a Customer Product/Process  
Change Notification (CPCN). Philips Semiconductors assumes no  
responsibility or liability for the use of any of these products, conveys no  
licence or title under any patent, copyright, or mask work right to these  
19. Trademarks  
Nexperia – is a trademark of Koninklijke Philips Electronics N.V.  
Dolby Pro Logic,Virtual Dolby Digital and Virtual Dolby Surround are  
trademarks of Dolby Laboratories |nc.  
BBE – is a registered trademark of BBE Sound Inc.  
dbx – is a registered trademark of Carillon Electronics Corp.  
20. Contact information  
For additional information, please visit http://www.semiconductors.philips.com  
For sales office addresses, send an email to: [email protected]  
9397 750 13928  
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.  
Product data  
Rev. 03 – 23 August 2004  
30 of 31  
 
                 
PNX2000  
Philips Semiconductors  
Audio video input processor  
21. Contents  
13.1  
Introduction to soldering surface mount  
© Koninklijke Philips Electronics N.V. 2004  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior  
written consent of the copyright owner. The information presented in this document does  
not form part of any quotation or contract, is believed to be accurate and reliable and may  
be changed without notice. No liability will be accepted by the publisher for any  
consequence of its use. Publication thereof does not convey nor imply any license under  
patent- or other industrial or intellectual property rights.  
Date of release: 23 August 2004  
Document order number: 9397 750 13928  
Published in Netherlands  
 

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